The University Lecture on “Energy-Efficient Deep Learning Accelerator: From Algorithm to Architecture” will take place as follows:
Date: 20 Apr 2018 (Friday)
Time: 11:00am - 12:00pm
Venue: N21-G013, Lecture Hall, Research Building, University of Macau
The speaker is:
Prof. Chi-Ying Tsui, Professor, Department of Electronic and Computer Engineering, HKUST
Associate Dean of Engineering (Undergraduate Studies)
The Lecture is:
Energy-Efficient Deep Learning Accelerator: From Algorithm to Architecture
Deep learning algorithm has become the main stream for a wide range of machine learning applications, including computer vision (CV), natural language processing (NLP), and robotics. While deep learning algorithm outperforms many other state-of-the-art AI algorithms, the high computation and storage complexity pose a challenge to the extensive deployment in the energy-stringent embedded applications. In this talk, we will explore how algorithmic and architectural co-design can be used to design energy efficient hardware accelerator for the inference phase of the deep neural networks (DNN). We propose SparseNN, a full-distributed architecture using Network-on-Chip (NoC) and exploiting the sparsity of the DNN to optimize the energy efficiency. In addition, we also address the issue of large memory footprints for the deep learning algorithm by compressing the weights of the neural network using a block hashing compressing technique. The corresponding ASIC architecture for the block hashing neural network will also be presented. The design is implemented and demonstrated on an FPGA platform. We will also discuss the use of an emerging memory device, Resistive RAM (RRAM), as an in-memory computing device for DNN architecture to address the memory wall issue.
Chi-Ying Tsui received his B.S. degree in Electrical Engineering from the University of Hong Kong and Ph.D. degree in Computer Engineering from the University of Southern California in 1994. He joined the Department of Electronic and Computer Engineering of Hong Kong University of Science and Technology in 1994 and is currently a full professor in the department and the Associate Dean of the School of Engineering.
His research interests include designing VLSI architectures for machine learning, digital baseband for wireless applications and low power applications, developing energy harvesting and power management circuits and techniques for ultra-low power embedded systems. He has published more than 200 referred publications and holds 10 US patents on power management, VLSI and multimedia systems. He received the best paper awards from the IEEE Transactions on VLSI Systems, IEEE ISCAS, IEEE/ACM ISLPED, IEEE DELTA and IEEE/ACM CODES. He also received the Design Awards in the IEEE ASP-DAC University Design Contest in 2004 and 2006.
For more details, kindly find the event poster, abstract and bio.