ChenYan Cai(Homepage)

ChenYan Cai

蔡辰燕

Joy

DCSP Research Line - Research Assistant


AwardsTotal: 3
  1. 3. Yang Jiang, Xiaofeng Yu, ChenYan Cai, "Third Prize for the Final Year Project Supervised (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)", “Challenge Cup” National Intervarsity Science and Technology Competition, China, Nov-2009
  2. 2. Yang Jiang, Xiaofeng Yu, ChenYan Cai, "Champion for the Final Year Project Supervised (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)", 2009 IEEE Project Competitions, Macau, Sep-2009
  3. 1. Yang Jiang, Xiaofeng Yu, ChenYan Cai, "3rd Class Award (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)", The Challenging Cup (挑戰盃) China National University Students Project Competition, , Apr-2009
Journals and MagazinesTotal: 1
  1. 1. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters", Analog Integrated Circuits and Signal Processing, Springer, Jul-2013.
Conference Papers and PresentationsTotal: 6
  1. 6. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 257-260, Nov-2012.
  2. 5. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012, pp 1096-1099, Aug-2012.
  3. 4. Yang Jiang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  4. 3. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  5. 2. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec-2010.
  6. 1. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", IEEE International Conference on Electronics, Circuits and Systems (ICECS, pp. 547-550, Dec-2010.



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