Yan Zhu(Homepage)

Yan Zhu

諸嫣

Julia

Email:yanzhu@umac.mo

Assistant Professor

Contact Hour: Mon 10:00-13:00, Wed 10:00-13:00

 

 

 

For her citation of publications, please visit:  https://scholar.google.com/citations?hl=en&user=fsX31qEAAAAJ


AwardsTotal: 5
  1. 5. Seng-Pan U, Yan Zhu, Sai Weng Sin, Chi Hang Chan, "Technological Invention Award-Third Prize(High Performance Wideband Data Conversion Interfaces for a Evolving Informative World)", The Science and Technology Development Fund(FDCT), Macau, Oct-2016
  2. 4. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, "Second-Class Award in the Technology Invention Award Category(Research and Development of Comprehensive and Advanced Data Conversion Platforms in Nanometer CMOS Technology)", The Science and Technology Development Fund(FDCT), Macau, Nov-2014
  3. 3. Yan Zhu, "Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012", FDCT, Macau, Oct-2012
  4. 2. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)", 2012 IEEE Symposium on VLSI Circuits – VLSI 2012, Honolulu, Hawai, USA, Jun-2012
  5. 1. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)", IEEE Asian Solid-State Circuits Conference, Jeju, South Korea, Nov-2011
Patents and Technology TransferTotal: 5
  1. 5. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption", US Patent, Granted Number: 8,427,355, Apr, 2013
  2. 4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Cascade Analog to Digital Converting System", US Patent, Application Number: 13/198,856, Granted Number: 8,466,823, Jun, 2013
  3. 3. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "Analog to Digital Converter Circuit", Taiwan Patent, Application Number: 100107757, Granted Number: 201242261, Mar, 2014
  4. 2. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Sampling front-end for analog to digital converter", US patent, Application Number: 13/915,949, Granted Number: 8,947,283, Feb, 2015
  5. 1. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "N-Bits Successive Approximation Register Analog-to-Digital Converting System", US Patent, Granted Number: 8,344,931, Jan, 2013
Journals and MagazinesTotal: 19
  1. 19. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  2. 18. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  3. 17. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Oct-2016.
  4. 16. Yan Lu, Cheng Li, Yan Zhu, Mo Huang, Seng-Pan U, R. P. Martins, "A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS", Electronics Letters, Aug-2016.
  5. 15. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jul-2016.
  6. 14. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Apr-2016.
  7. 13. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS", IEEE Journal of Solid-State Circuits, Feb-2016.
  8. 12. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016.
  9. 11. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016.
  10. 10. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2015.
  11. 9. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, "Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jun-2015.
  12. 8. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014.
  13. 7. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013.
  14. 6. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Journal of Solid-State Circuits, Aug-2013.
  15. 5. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012.
  16. 4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC", IEEE Transactions on CAS – Part II: Express Briefs, Aug-2010.
  17. 3. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010.
  18. 2. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs", Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems, Apr-2010.
  19. 1. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS", IEEE Trans. on Circuits and System II – Express Briefs, Jan-2010.
Conference Papers and PresentationsTotal: 28
  1. 28. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-284, Feb-2017.
  2. 27. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, "A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 145-148 (highlighted paper and invited to JSSC special issue), Nov-2016.
  3. 26. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016.
  4. 25. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016.
  5. 24. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015.
  6. 23. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015.
  7. 22. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC", IEEE European Solid-State Circuit Conference – (ESSCIRC), pp.211-214, Sep-2014.
  8. 21. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 69-72, Nov-2013.
  9. 20. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013.
  10. 19. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 153-156, Nov-2012.
  11. 18. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, pp 1-4, Aug-2012.
  12. 17. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012.
  13. 16. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012.
  14. 15. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011.
  15. 14. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011.
  16. 13. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, "Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs", Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov-2011.
  17. 12. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  18. 11. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, pp. 218-221, Sep-2010.
  19. 10. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug-2010.
  20. 9. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs", IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp. 607-611, May-2010.
  21. 8. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 392-395, Nov-2009.
  22. 7. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, "On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator", in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov-2009.
  23. 6. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, "Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 333-336, Nov-2009.
  24. 5. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec-2008.
  25. 4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec-2008.
  26. 3. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs", in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008, pp. 642-645, Sep-2008.
  27. 2. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier", ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Aug-2008.
  28. 1. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs", in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008, pp. 922-925, Aug-2008.
ThesesTotal: 1
  1. 1. WenLan Wu, "Monotonic Multi-Switching Method for Ultra-Low-Voltage Energy Efficient SAR ADCs", , , Jun-2013



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