Sai Weng Sin(Homepage)

Sai Weng Sin

冼世榮

Terry

Email:terryssw@umac.mo

Teaching Coordinator / Data Conversion Research Line Coordinator

For a complete CV, please go to http://www.fst.umac.mo/en/staff/fstsws.html


AwardsTotal: 22
  1. 22. Seng-Pan U, Yan Zhu, Sai Weng Sin, Chi Hang Chan, "Technological Invention Award-Third Prize(High Performance Wideband Data Conversion Interfaces for a Evolving Informative World)", The Science and Technology Development Fund(FDCT), Macau, Oct-2016
  2. 21. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, "Second-Class Award in the Technology Invention Award Category(Research and Development of Comprehensive and Advanced Data Conversion Platforms in Nanometer CMOS Technology)", The Science and Technology Development Fund(FDCT), Macau, Nov-2014
  3. 20. R. P. Martins, Seng-Pan U, Pui In Mak, Sai Weng Sin, "Second Class Award of the Macao Science and Technology Award - Technological Invention category", The Science and Technology Development Fund, Macau, Oct-2012
  4. 19. Seng-Pan U, Pui In Mak, Sai Weng Sin, "Special Award, the Macao Science and Technology Award 2012", FDCT, Macau, Oct-2012
  5. 18. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)", 2012 IEEE Symposium on VLSI Circuits – VLSI 2012, Honolulu, Hawai, USA, Jun-2012
  6. 17. Seng-Pan U, Pui In Mak, Sai Weng Sin, "National Science and Technology Progress Awards", Ministry of Science and Technology of the People's Republic of China, Beijing, Jan-2012
  7. 16. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)", IEEE Asian Solid-State Circuits Conference, Jeju, South Korea, Nov-2011
  8. 15. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Bronze Leaf Certificate (A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture)", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), Macau, Oct-2011
  9. 14. Sai Weng Sin, Pengyu Yan, Zhiyuan Chen, "1st Runner-Up for the Final Year Project", 2011 IEEE Project Competitions, Macau, Jun-2011
  10. 13. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)", Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011, San Francisco, USA., Feb-2011
  11. 12. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Award for Research Excellence 2007-2009", University of Macau, , Apr-2010
  12. 11. Sai Weng Sin, Seng-Pan U, R. P. Martins, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, "Bronze Leaf Certificate (Comparator-Based Successive Folding ADC)", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia 2009), , Sep-2009
  13. 10. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Merit Paper Award (Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter)", The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), , Apr-2009
  14. 9. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "1st Runner-up (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)", The Institution of Engineering and Technology, Hong Kong (Undergraduate Section - IET Young Members Exhibition and Conference 2008), , Dec-2008
  15. 8. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Champion in IEEE Project Competitions (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)", IEEE Macau Society, , Nov-2008
  16. 7. Sai Weng Sin, "Chipidea Microelectronics Prize – Postgraduate Level, for the outstanding academic and research achievement in Microelectronics", University of Macau, , Nov-2008
  17. 6. Sai Weng Sin, "Chipidea Microelectronics Prize (Generalized Low-Voltage Circuit Design Techniques for Very High-Speed Time-Interleaved Pipelined ADC)", Chipidea Microelectronics, Macau, , Apr-2008
  18. 5. Sai Weng Sin, "Student Paper Contest Award", International Symposium on Circuits and Systems (ISCAS’2005), , May-2005
  19. 4. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Selected Student Paper Scholarship (Paper Title I: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits”, Paper Title II: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits” )", IEEE International Symposium on Circuits and Systems (ISCAS), , May-2005
  20. 3. Sai Weng Sin, "Excellent Scholarship of CEM (Companhia de Electricidade de Macau) for the outstanding academic achievement", University of Macau, , Aug-2001
  21. 2. Sai Weng Sin, "Excellent Scholarship of Macau Foundation for the outstanding academic achievement", University of Macau, , Aug-2001
  22. 1. Sai Weng Sin, "Excellent Scholarship of HSBC (The Hongkong and Shanghai Banking Corporation) for the outstanding academic achievement", University of Macau, , Aug-2000
Patents and Technology TransferTotal: 7
  1. 7. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption", US Patent, Granted Number: 8,427,355, Apr, 2013
  2. 6. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", US Patent, Granted Number: 8,441,295, May, 2013
  3. 5. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Cascade Analog to Digital Converting System", US Patent, Application Number: 13/198,856, Granted Number: 8,466,823, Jun, 2013
  4. 4. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "Analog to Digital Converter Circuit", Taiwan Patent, Application Number: 100107757, Granted Number: 201242261, Mar, 2014
  5. 3. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", Taiwan Patent, Application Number: 100116148, Granted Number: 201246793, Mar, 2014
  6. 2. Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Mixed signal controller", US patent, Application Number: 15/218070, , Jul 2017
  7. 1. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "N-Bits Successive Approximation Register Analog-to-Digital Converting System", US Patent, Granted Number: 8,344,931, Jan, 2013
Journals and MagazinesTotal: 30
  1. 30. Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting", IEEE Transactions on Circuits and Systems II, Feb-2017.
  2. 29. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  3. 28. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  4. 27. Arshad Hussain, Sai Weng Sin, Chi Hang Chan, Seng-Pan U, Franco Maloberti, R. P. Martins, "Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017.
  5. 26. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Oct-2016.
  6. 25. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Wing-Hung Ki, "Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators", IEEE Transactions on Circuits and Systems II, Sep-2016.
  7. 24. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS", in Journal of Semiconductor Technology and Science, Aug-2016.
  8. 23. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation", IEEE Transactions on Circuits and Systems II, Jul-2016.
  9. 22. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Apr-2016.
  10. 21. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016.
  11. 20. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016.
  12. 19. Wen-Liang Zheng, Chi-Seng Lam, Wen-Ming Zheng, Sai Weng Sin, Ning-Yi Dai, Man-Chung Wong, Seng-Pan U, R. P. Martins, "DCM operation analysis of KY converter", IET Electronics Letters, Nov-2015.
  13. 18. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading", IEEE Transactions on Power Electronics, Oct-2015.
  14. 17. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2015.
  15. 16. Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications", IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063, Jul-2015.
  16. 15. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014.
  17. 14. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013.
  18. 13. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Journal of Solid-State Circuits, Aug-2013.
  19. 12. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters", Analog Integrated Circuits and Signal Processing, Springer, Jul-2013.
  20. 11. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012.
  21. 10. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC", IEEE Journal of Solid-State Circuits, Nov-2012.
  22. 9. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC", IEEE Transactions on CAS – Part II: Express Briefs, Aug-2010.
  23. 8. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010.
  24. 7. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs", Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems, Apr-2010.
  25. 6. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom", IET Proceedings - Circuits, Devices and Systems, Jan-2010.
  26. 5. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS", IEEE Trans. on Circuits and System II – Express Briefs, Jan-2010.
  27. 4. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS", 澳門機電工程專業協會(APEMEM)會刊(2007-2008), Apr-2009.
  28. 3. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps", IEEE Transactions on Circuits and Systems I - Regular Papers, Sep-2008.
  29. 2. Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch", IEEE Trans. on Circuits and Systems II – Express Briefs, Jul-2008.
  30. 1. Seng-Pan U, Sai Weng Sin, R. P. Martins, "Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects", IEEE Transactions on Instrumentation and Measurement, Aug-2004.
Conference Papers and PresentationsTotal: 87
  1. 87. Wei Li, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications", International Symposium on Integrated Circuits, , Dec-2016.
  2. 86. Yuan Ren, Sai Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, R. P. Martins, "A high DR multi-channel stage-shared hybrid sigma-delta modulator for integrated power electronics controller front-end", IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, Nov-2016.
  3. 85. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016.
  4. 84. Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U-Fat Chio, Sai Weng Sin, R. P. Martins, "An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology", . IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 421-424, Sep-2016.
  5. 83. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016.
  6. 82. Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A high resolution multi-bit incremental converter insensitive to DAC mismatch error", Ph.D Research in Micro-electronics & Electronics (PRIME), , Jun-2016.
  7. 81. Wen-Ming Zheng, Chi-Seng Lam, Sai Weng Sin, Yan Lu, Man-Chung Wong, Seng-Pan U, R. P. Martins, "Capacitive floating level shifter: Modeling and design", IEEE Region 10 Conference (TENCON), Macau, China, pp. 1-6, Nov-2015.
  8. 80. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, pp.1-4, Nov-2015.
  9. 79. Ka-Fai Chan, Chi-Seng Lam, Wen-Liang Zheng, Wen-Ming Zheng, Sai Weng Sin, Man-Chung Wong, "Generalized type III controller design interface for dc-dc converters", The IEEE Region 10 Conference (TENCON 2015), Macau, China, pp. 1 – 6, Nov-2015.
  10. 78. Haojuan Dai, Yan Lu, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Review and Design of the On-Chip Rectifiers for RF Energy Harvesting", IEEE International Wireless Symposium (IWS), pp. 1-4, Mar-2015.
  11. 77. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015.
  12. 76. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015.
  13. 75. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 364-365, Feb-2015.
  14. 74. Da Feng, Sai Weng Sin, E. Bonizzoni, Franco Maloberti, "Time interleaved current steering DAC for ultra-high conversion rate", IEEE Ph.D Research in Micro-electronics & Electronics (PRIME), pp. 1-4, Jun-2014.
  15. 73. Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration", IEEE Asian Solid-State Circuit Conference – (A-SSCC),, pp 77-80, Nov-2013.
  16. 72. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), pp 665-668, Aug-2013.
  17. 71. Yan Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW", IEEE International Symposium on Circuits and Systems (ISCAS), pp 373-376, May-2013.
  18. 70. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013.
  19. 69. Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 29-32, Dec-2012.
  20. 68. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 33-36, Dec-2012.
  21. 67. WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 268-271, Dec-2012.
  22. 66. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 257-260, Nov-2012.
  23. 65. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 153-156, Nov-2012.
  24. 64. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 377-380, Sep-2012.
  25. 63. Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 265-268, Sep-2012.
  26. 62. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012, pp 1096-1099, Aug-2012.
  27. 61. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, pp 1-4, Aug-2012.
  28. 60. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012.
  29. 59. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012.
  30. 58. Tao He, Yang Jiang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer", IEEE Int. Symposium on Circuits and Systems (ISCAS), pp 65-69, May-2012.
  31. 57. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011.
  32. 56. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 73-76, Nov-2011.
  33. 55. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011.
  34. 54. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, "Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs", Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov-2011.
  35. 53. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation", International SoC Design Conference – ISOCC, pp. 76-79, Nov-2011.
  36. 52. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), Macao, China, pp. 25-28, Oct-2011.
  37. 51. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture", Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimaAsia), pp. 1-4, Oct-2011.
  38. 50. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A time-efficient dither-injection scheme for pipelined SAR ADC", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct-2011.
  39. 49. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "NTF Zero Compensation Technique For Passive Sigma-Delta Modulator", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-85, Oct-2011.
  40. 48. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Sep-2011.
  41. 47. Zhijie Chen, Peng Zhang, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  42. 46. Yang Jiang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  43. 45. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  44. 44. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  45. 43. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  46. 42. Peng Zhang, Zhijie Chen, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC", ", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  47. 41. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters", 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, Jun-2011.
  48. 40. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS", IEEE International Solid-State Circuit Conference (ISSCC),, pp. 188-189, Feb-2011.
  49. 39. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec-2010.
  50. 38. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec-2010.
  51. 37. Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications", IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 878-881, Dec-2010.
  52. 36. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", IEEE International Conference on Electronics, Circuits and Systems (ICECS, pp. 547-550, Dec-2010.
  53. 35. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation", IEEE Asian Solid-State Circuits Conference – ASSCC 2010, pp. 1-4, Nov-2010.
  54. 34. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 115-118, Sep-2010.
  55. 33. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, pp. 218-221, Sep-2010.
  56. 32. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug-2010.
  57. 31. Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug-2010.
  58. 30. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 566-569, Aug-2010.
  59. 29. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug-2010.
  60. 28. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Background Amplifier Offset Calibration Technique for High-Resolution Pipelined ADC", IEEE International NEWCAS Conference – NEWCAS 2010, pp. 41-44, Jun-2010.
  61. 27. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs", IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp. 607-611, May-2010.
  62. 26. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC", Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010, , Feb-2010.
  63. 25. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 392-395, Nov-2009.
  64. 24. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, "On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator", in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov-2009.
  65. 23. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, "Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 333-336, Nov-2009.
  66. 22. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 86-89, Aug-2009.
  67. 21. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Comparator-Based Successive Folding ADC", IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 117-120, Jan-2009.
  68. 20. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec-2008.
  69. 19. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec-2008.
  70. 18. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec-2008.
  71. 17. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs", in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008, pp. 642-645, Sep-2008.
  72. 16. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier", ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Aug-2008.
  73. 15. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs", in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008, pp. 922-925, Aug-2008.
  74. 14. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications", Proceedings of RIUPEEEC (Macao, China), pp. 105-108, Jul-2006.
  75. 13. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter", Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp. 133-136, Jul-2006.
  76. 12. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits", in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3794-3797, May-2006.
  77. 11. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4305-4308, May-2006.
  78. 10. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps", in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 398-401, Jul-2005.
  79. 9. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits", in Proc.of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 1585-1588, May-2005.
  80. 8. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 1581-1584, May-2005.
  81. 7. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems", Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004, pp. 172-175, Oct-2004.
  82. 6. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems", in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. I-369 – I-372, May-2004.
  83. 5. Seng-Pan U, Sai Weng Sin, R. P. Martins, "Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches", in Proc. of IEEE Instrumentation and Measurement Technology Conference (IMTC), vol. 2, pp. 1298-1301, May-2003.
  84. 4. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output", in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS), vol. 1, pp. I-129 – I-132, May-2003.
  85. 3. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals", in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 6, pp. VI_253-VI_256, Apr-2003.
  86. 2. Sai Weng Sin, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam, R. P. Martins, "An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors", in Proceedings of IEEE International Conference on ASIC - ASICON’2001, pp. 670-672, Oct-2001.
  87. 1. Sai Weng Sin, Lai Keng Chong, Chiang Kuok Vai, Choi Wai Wa, K.W.Tam, R. P. Martins, "A New IMD3 Reduction Approach based on Composite Effect of g""m and g""ds,""", Proceedings of IEEE CAS Workshop on Wireless Communications and Networking, South Bend, Indiana, , Aug-2001.
Books and Book ChaptersTotal: 1
  1. 1. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters", Analog Circuits and Signal Processing, Springer, Oct-2010, 978-90-481-9709-5
ThesesTotal: 1
  1. 1. WenLan Wu, "Monotonic Multi-Switching Method for Ultra-Low-Voltage Energy Efficient SAR ADCs", , , Jun-2013



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