Seng-Pan U(Homepage)

Seng-Pan U

余成斌

Ben

Email:benspu@umac.mo

Deputy Director

For a complete CV, please go to http://www.fst.umac.mo/en/staff/fstspu.html


AwardsTotal: 46
  1. 46. Seng-Pan U, Yan Zhu, Sai Weng Sin, Chi Hang Chan, "Technological Invention Award-Third Prize(High Performance Wideband Data Conversion Interfaces for a Evolving Informative World)", The Science and Technology Development Fund(FDCT), Macau, Oct-2016
  2. 45. Mo Huang, Yan Lu, Xiao-ming Xiong, Seng-Pan U, R. P. Martins, "Professional Award (An All-Factor Modulation Bandwidth Extension Technique for Delta-Sigma PLL Transmitter)", IEEE Region 10, Macau, Nov-2015
  3. 44. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, "Second-Class Award in the Technology Invention Award Category(Research and Development of Comprehensive and Advanced Data Conversion Platforms in Nanometer CMOS Technology)", The Science and Technology Development Fund(FDCT), Macau, Nov-2014
  4. 43. Seng-Pan U, "Scientific Chinese of the Year 2012 (Information Technology and Electronics category)", SCICHI, Beijing, Jun-2013
  5. 42. Seng-Pan U, "2013 IEEE Solid-State Circuits Society Macao Chapter - Best Chapter Award (World)", IEEE Solid-State Circuits Society, San Francisco, USA., Feb-2013
  6. 41. R. P. Martins, Seng-Pan U, Pui In Mak, Sai Weng Sin, "Second Class Award of the Macao Science and Technology Award - Technological Invention category", The Science and Technology Development Fund, Macau, Oct-2012
  7. 40. Seng-Pan U, Pui In Mak, Sai Weng Sin, "Special Award, the Macao Science and Technology Award 2012", FDCT, Macau, Oct-2012
  8. 39. Kuok Hang Mok, Weng Ieng Mok, Ka Hou Ao Ieong, Seng-Pan U, lu Leong Chan, "Second Class Award of Science and Technology Progress Award 2012", FDCT, Macau, Oct-2012
  9. 38. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)", 2012 IEEE Symposium on VLSI Circuits – VLSI 2012, Honolulu, Hawai, USA, Jun-2012
  10. 37. Seng-Pan U, Pui In Mak, Sai Weng Sin, "National Science and Technology Progress Awards", Ministry of Science and Technology of the People's Republic of China, Beijing, Jan-2012
  11. 36. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)", IEEE Asian Solid-State Circuits Conference, Jeju, South Korea, Nov-2011
  12. 35. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Bronze Leaf Certificate (A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture)", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), Macau, Oct-2011
  13. 34. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)", Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011, San Francisco, USA., Feb-2011
  14. 33. Seng-Pan U, "Honorary Title of Value of 2010 ( An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement)", Macau SAR Government, , Dec-2010
  15. 32. Seng-Pan U, R. P. Martins, "HLHL Scientific and Technological Innovation Award (First from Macau)", He Leung Ho Lee Foundation, , Sep-2010
  16. 31. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Award for Research Excellence 2007-2009", University of Macau, , Apr-2010
  17. 30. Sai Weng Sin, Seng-Pan U, R. P. Martins, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, "Bronze Leaf Certificate (Comparator-Based Successive Folding ADC)", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia 2009), , Sep-2009
  18. 29. R. P. Martins, Seng-Pan U, Pui In Mak, "2009 World-Chapter of the Year", IEEE Circuits And Systems Society, IEEE Macau Joint-Chapter on CAS/COM, Founding Chapter Chair 2005-2008, , May-2009
  19. 28. Ka Hou Ao Ieong, Seng-Pan U, R. P. Martins, "Merit Paper Award (Design of a 1-V 10-bit 120-MS/s Current-Steering DAC with Transient-Improved Technique)", The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), , Apr-2009
  20. 27. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Merit Paper Award (Novel Timing-Skew-Insensitive, Multi-Phase Clock Generation Scheme For Parallel Dac And N-Path Filter)", The 2006 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), , Apr-2009
  21. 26. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "1st Runner-up (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)", The Institution of Engineering and Technology, Hong Kong (Undergraduate Section - IET Young Members Exhibition and Conference 2008), , Dec-2008
  22. 25. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Champion in IEEE Project Competitions (A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique)", IEEE Macau Society, , Nov-2008
  23. 24. Pui In Mak, Seng-Pan U, R. P. Martins, "Silver Leaf Certificate (Multistandard-Compliant Receiver Architecture with low-voltage Implementation)", IEEE Ph.D. Research in Microelectronics and Electronics Conference – PRIME'2005, École Polytechnique Fédéral de Lausanne - EPFL, Lausanne, Switzerland., Jul-2005
  24. 23. Pui In Mak, R. P. Martins, Seng-Pan U, "Award for Second Place / Conceptual Architecture Category (A 1V IEEE 802.11a/b/g-Compliant Receiver IF-to-Baseband Chip in 0.35µm CMOS for Low-Cost Wireless SiP)", 42nd Edition of Design Automation Conference – DAC’2005 (Anaheim), California, USA., Jun-2005
  25. 22. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Selected Student Paper Scholarship (Paper Title I: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits”, Paper Title II: Sai-Weng Sin, Seng-Pan U and R.P.Martins, “A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits” )", IEEE International Symposium on Circuits and Systems (ISCAS), , May-2005
  26. 21. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "Merit Paper Award (On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC)", awarded from The 2005 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), , Apr-2005
  27. 20. Seng-Pan U, "Lecture Fellowship", K. C. Wong Education Foundation, , Apr-2005
  28. 19. Seng-Pan U, "Nomination of “The 2005 National Best Doctoral Dissertations”", the Ministry of Education and State Academic Degrees Committee of the State Council., , Apr-2005
  29. 18. Seng-Pan U, "FST Teaching Award 2004", University of Macau, Macao, China, Apr-2005
  30. 17. Pui In Mak, Seng-Pan U, R. P. Martins, "Best Paper Award (A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver)", IEEJ (7th) International Analog VLSI Workshop (AVLSIWS 2004), , Jul-2004
  31. 16. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, ""2nd Prize” in Student Paper Contest (Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC)", IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2004), , Jul-2004
  32. 15. Pui In Mak, Seng-Pan U, R. P. Martins, "Outstanding Student Paper Award (A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver)", The 5th International Conference on ASIC, , Oct-2003
  33. 14. Seng-Pan U, "Young Researcher Prize 2003", International Institute of Macau, Macao, China, Apr-2003
  34. 13. Seng-Pan U, "The Most Favorite Teacher in 3rd- and 4th-year of EEE", Faculty of Science and Technology Students’ Association, , Apr-2003
  35. 12. Seng-Pan U, "The Most Favorite Teacher in 1st- and 2nd-year of EEE", Faculty of Science and Technology Students’ Association, , Apr-2003
  36. 11. Seng-Pan U, "The Most Favorite Teacher in EEE", Faculty of Science and Technology Students’ Association, Macao, China, Apr-2002
  37. 10. Seng-Pan U, "Very Good with Honor and Distinction", University of Macau for Ph.D. degree (Highest honor), Macao, China, Apr-2002
  38. 9. Seng-Pan U, "The Outstanding Alumni Award", Hou Kong Middle School of Macau, , Apr-2002
  39. 8. Seng-Pan U, "Excellent Young Scholar Award 2001 (First Prize)", University of Macau, , Apr-2001
  40. 7. Seng-Pan U, "Excellent Research Scholarship", Center of Microsystems, Instituto Superior Técnico (IST), Universidade Técnica de Lisboa, Portugal, Portugal, Apr-2000
  41. 6. Seng-Pan U, "Research Scholarship", Fundação Oriente, , Apr-1999
  42. 5. Seng-Pan U, "Certificate of Merit", Institution of Electrical Engineers (IEE) for IEE (HK) Younger Members Section Paper Contest 97/98 (Postgraduate Session), , Apr-1999
  43. 4. Seng-Pan U, "Certificate of Merit", Institute of Electrical and Electronic Engineers (IEEE) for 1998 IEEE Postgraduate Student Paper Contest, Hong Kong, China, Apr-1998
  44. 3. Seng-Pan U, "Very Good with Honor and Distinction", University of Macau for postgraduate study (Highest honor), , Apr-1997
  45. 2. Seng-Pan U, "Excellent University Graduate", Jinan University, , Apr-1991
  46. 1. Seng-Pan U, "Province Outstanding University Scholar Award", the Guangdong Return Overseas Chinese Association, , Apr-1990
Patents and Technology TransferTotal: 11
  1. 11. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection for Wireless Transmitter Front-Ends", US Patent, Granted Number: 8,019,290, Sep. 13, 2011
  2. 10. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption", US Patent, Granted Number: 8,427,355, Apr, 2013
  3. 9. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", US Patent, Granted Number: 8,441,295, May, 2013
  4. 8. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Cascade Analog to Digital Converting System", US Patent, Application Number: 13/198,856, Granted Number: 8,466,823, Jun, 2013
  5. 7. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "Analog to Digital Converter Circuit", Taiwan Patent, Application Number: 100107757, Granted Number: 201242261, Mar, 2014
  6. 6. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", Taiwan Patent, Application Number: 100116148, Granted Number: 201246793, Mar, 2014
  7. 5. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Sampling front-end for analog to digital converter", US patent, Application Number: 13/915,949, Granted Number: 8,947,283, Feb, 2015
  8. 4. Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Mixed signal controller", US patent, Granted, No. 9,692,232, Jun 2017
  9. 3. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "N-Bits Successive Approximation Register Analog-to-Digital Converting System", US Patent, Granted Number: 8,344,931, Jan, 2013
  10. 2. Pui In Mak, Seng-Pan U, R. P. Martins, "Switched Current-Resistor Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same", US Patent, Granted Number: 8,229,382, Jul, 2012
  11. 1. Pui In Mak, Seng-Pan U, R. P. Martins, "DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same", US Patent, Granted Number: 7,948,309, May, 2011
Journals and MagazinesTotal: 48
  1. 48. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator", IEEE Journal of Solid-State Circuits, Jan-2018.
  2. 47. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Sub-1V 78-nA Bandgap Reference with Curvature Compensation", Elsevier Microelectronics Journal, May-2017.
  3. 46. Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting", IEEE Transactions on Circuits and Systems II, Feb-2017.
  4. 45. Yan Lu, Mo Huang, Lin Cheng, Wing-Hung Ki, Seng-Pan U, R. P. Martins, "A Dual-Output Wireless Power Transfer System with Active Rectifier and Three-Level Operation", IEEE Transactions on Power Electronics, Feb-2017.
  5. 44. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  6. 43. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Feb-2017.
  7. 42. Yi-Wei Tan, Chi-Seng Lam, Sai Weng Sin, Man-Chung Wong, Seng-Pan U, R. P. Martins, "DCM operation analysis of 3-level boost converters", ”, IET Electronics Letters, Feb-2017.
  8. 41. Arshad Hussain, Sai Weng Sin, Chi Hang Chan, Seng-Pan U, Franco Maloberti, R. P. Martins, "Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017.
  9. 40. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Oct-2016.
  10. 39. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Wing-Hung Ki, "Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators", IEEE Transactions on Circuits and Systems II, Sep-2016.
  11. 38. Yan Lu, Cheng Li, Yan Zhu, Mo Huang, Seng-Pan U, R. P. Martins, "A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS", Electronics Letters, Aug-2016.
  12. 37. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS", in Journal of Semiconductor Technology and Science, Aug-2016.
  13. 36. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation", IEEE Transactions on Circuits and Systems II, Jul-2016.
  14. 35. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jul-2016.
  15. 34. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Apr-2016.
  16. 33. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS", IEEE Journal of Solid-State Circuits, Feb-2016.
  17. 32. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016.
  18. 31. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016.
  19. 30. Wen-Liang Zheng, Chi-Seng Lam, Wen-Ming Zheng, Sai Weng Sin, Ning-Yi Dai, Man-Chung Wong, Seng-Pan U, R. P. Martins, "DCM operation analysis of KY converter", IET Electronics Letters, Nov-2015.
  20. 29. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading", IEEE Transactions on Power Electronics, Oct-2015.
  21. 28. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2015.
  22. 27. Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications", IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063, Jul-2015.
  23. 26. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, "Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jun-2015.
  24. 25. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014.
  25. 24. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013.
  26. 23. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Journal of Solid-State Circuits, Aug-2013.
  27. 22. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters", Analog Integrated Circuits and Signal Processing, Springer, Jul-2013.
  28. 21. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012.
  29. 20. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC", IEEE Journal of Solid-State Circuits, Nov-2012.
  30. 19. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC", IEEE Transactions on CAS – Part II: Express Briefs, Aug-2010.
  31. 18. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010.
  32. 17. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs", Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems, Apr-2010.
  33. 16. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom", IET Proceedings - Circuits, Devices and Systems, Jan-2010.
  34. 15. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS", IEEE Trans. on Circuits and System II – Express Briefs, Jan-2010.
  35. 14. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS", 澳門機電工程專業協會(APEMEM)會刊(2007-2008), Apr-2009.
  36. 13. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps", IEEE Transactions on Circuits and Systems I - Regular Papers, Sep-2008.
  37. 12. Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch", IEEE Trans. on Circuits and Systems II – Express Briefs, Jul-2008.
  38. 11. Pui In Mak, Seng-Pan U, R. P. Martins, "On the Design of Programmable-Gain Amplifier with Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems", ", IEEE Transactions on Circuits and Systems – I: Regular Papers, Mar-2008.
  39. 10. Pui In Mak, Seng-Pan U, R. P. Martins, "An Experimental 1-V Flexible-IF CMOS Analogue-Baseband Chain for IEEE 802.11a/b/g WLAN Receivers", IET Proceedings - Circuits, Devices and Systems, Dec-2007.
  40. 9. Pui In Mak, Seng-Pan U, R. P. Martins, "Transceiver Architecture Selection - Review, State-of-the-Art Survey and Case Study", IEEE Circuits and Systems Magazine, Jun-2007.
  41. 8. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends", IEEE Transactions on Circuits and Systems-I, Regular Paper, Jul-2005.
  42. 7. Seng-Pan U, Sai Weng Sin, R. P. Martins, "Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects", IEEE Transactions on Instrumentation and Measurement, Aug-2004.
  43. 6. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection Technique by Programmable Digital-Double Quadrature Sampling for Complex Low-IF Receivers", IEE Electronics Letters, May-2003.
  44. 5. Seng-Pan U, R. P. Martins, J.E.Franca, "A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter with 320-MHz Output for DDFS System in 0.35-µm CMOS", IEEE Journal of Solid-State Circuits, Feb-2002.
  45. 4. Seng-Pan U, R. P. Martins, J.E.Franca, "Improved Switched-Capacitor Interpolators with Reduced Sample-and-Hold Effects", IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, Aug-2000.
  46. 3. Seng-Pan U, R. P. Martins, J.E.Franca, "Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation", IEE Electronics Letters, Feb-1999.
  47. 2. Seng-Pan U, R. P. Martins, J.E.Franca, "Impulse Sampled FIR Interpolation with SC Active-Delayed Block Polyphase Structures", IEE Electronics Letters, Mar-1998.
  48. 1. Seng-Pan U, R. P. Martins, J.E.Franca, "Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect", IEE Electronics Letters, May-1996.
Conference Papers and PresentationsTotal: 152
  1. 152. Xia Du, Chi-Seng Lam, Sai Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R. P. Martins, "A digital pwm controlled ky step-up converter based on frequency domain ΣΔ ADC", The 26th IEEE International Symposium on Industrial Electronics (ISIE 2017), , Jun-2017.
  2. 151. Xia Du, Chi-Seng Lam, Sai Weng Sin, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R. P. Martins, "
    A digital pwm controlled ky step-up converter based on passive sigma-delta modulator
    ", The IEEE International Future Energy Electronics Conference 2017 – ECCE Asia (IFEEC 2017-ECCE Asia), , Jun-2017.
  3. 150. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "A Reconfigurable Bidirectional Wireless Power Transceiver with Maximum Current Charging Mode and 58.6% Battery-to-Battery Efficiency", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), , Feb-2017.
  4. 149. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri-loop Control", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), , Feb-2017.
  5. 148. Junmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, R. P. Martins, "A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for Application Processors in 28nm CMOS", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), , Feb-2017.
  6. 147. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-284, Feb-2017.
  7. 146. Wei Li, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications", International Symposium on Integrated Circuits, , Dec-2016.
  8. 145. Yuan Ren, Sai Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, R. P. Martins, "A high DR multi-channel stage-shared hybrid sigma-delta modulator for integrated power electronics controller front-end", IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, Nov-2016.
  9. 144. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, "A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 145-148 (highlighted paper and invited to JSSC special issue), Nov-2016.
  10. 143. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "A Digital LDO with Transient Enhancement and Limit Cycle Oscillation Reduction", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Oct-2016.
  11. 142. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016.
  12. 141. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016.
  13. 140. Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A high resolution multi-bit incremental converter insensitive to DAC mismatch error", Ph.D Research in Micro-electronics & Electronics (PRIME), , Jun-2016.
  14. 139. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, pp.1-4, Nov-2015.
  15. 138. Mo Huang, Yan Lu, Xiao-ming Xiong, Seng-Pan U, R. P. Martins, "An All-Factor Modulation Bandwidth Extension Technique for Delta-Sigma PLL Transmitter", IEEE Region 10 Conference (TENCON), pp. 1-4. Professional Award, Nov-2015.
  16. 137. Wen-Ming Zheng, Chi-Seng Lam, Sai Weng Sin, Yan Lu, Man-Chung Wong, Seng-Pan U, R. P. Martins, "Capacitive floating level shifter: Modeling and design", IEEE Region 10 Conference (TENCON), Macau, China, pp. 1-6, Nov-2015.
  17. 136. Haojuan Dai, Yan Lu, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Review and Design of the On-Chip Rectifiers for RF Energy Harvesting", IEEE International Wireless Symposium (IWS), pp. 1-4, Mar-2015.
  18. 135. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015.
  19. 134. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015.
  20. 133. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 364-365, Feb-2015.
  21. 132. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC", IEEE European Solid-State Circuit Conference – (ESSCIRC), pp.211-214, Sep-2014.
  22. 131. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 69-72, Nov-2013.
  23. 130. Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration", IEEE Asian Solid-State Circuit Conference – (A-SSCC),, pp 77-80, Nov-2013.
  24. 129. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), pp 665-668, Aug-2013.
  25. 128. Yan Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW", IEEE International Symposium on Circuits and Systems (ISCAS), pp 373-376, May-2013.
  26. 127. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013.
  27. 126. Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 29-32, Dec-2012.
  28. 125. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 33-36, Dec-2012.
  29. 124. WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 268-271, Dec-2012.
  30. 123. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 257-260, Nov-2012.
  31. 122. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 153-156, Nov-2012.
  32. 121. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 377-380, Sep-2012.
  33. 120. Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 265-268, Sep-2012.
  34. 119. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012, pp 1096-1099, Aug-2012.
  35. 118. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, pp 1-4, Aug-2012.
  36. 117. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012.
  37. 116. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012.
  38. 115. Tao He, Yang Jiang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer", IEEE Int. Symposium on Circuits and Systems (ISCAS), pp 65-69, May-2012.
  39. 114. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011.
  40. 113. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 73-76, Nov-2011.
  41. 112. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011.
  42. 111. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, "Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs", Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov-2011.
  43. 110. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation", International SoC Design Conference – ISOCC, pp. 76-79, Nov-2011.
  44. 109. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), Macao, China, pp. 25-28, Oct-2011.
  45. 108. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture", Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimaAsia), pp. 1-4, Oct-2011.
  46. 107. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A time-efficient dither-injection scheme for pipelined SAR ADC", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct-2011.
  47. 106. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "NTF Zero Compensation Technique For Passive Sigma-Delta Modulator", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-85, Oct-2011.
  48. 105. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Sep-2011.
  49. 104. Yang Jiang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  50. 103. Zhijie Chen, Peng Zhang, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  51. 102. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  52. 101. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  53. 100. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  54. 99. Peng Zhang, Zhijie Chen, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC", ", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011.
  55. 98. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters", 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, Jun-2011.
  56. 97. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS", IEEE International Solid-State Circuit Conference (ISSCC),, pp. 188-189, Feb-2011.
  57. 96. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1011-1014, Dec-2010.
  58. 95. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 208-211, Dec-2010.
  59. 94. Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications", IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 878-881, Dec-2010.
  60. 93. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators", IEEE International Conference on Electronics, Circuits and Systems (ICECS, pp. 547-550, Dec-2010.
  61. 92. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation", IEEE Asian Solid-State Circuits Conference – ASSCC 2010, pp. 1-4, Nov-2010.
  62. 91. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 115-118, Sep-2010.
  63. 90. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, pp. 218-221, Sep-2010.
  64. 89. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug-2010.
  65. 88. Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug-2010.
  66. 87. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Level-Shifting Variable Current Charging Technique for High-Speed Comparator-Based Switched-Capacitor Circuits", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 566-569, Aug-2010.
  67. 86. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug-2010.
  68. 85. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Background Amplifier Offset Calibration Technique for High-Resolution Pipelined ADC", IEEE International NEWCAS Conference – NEWCAS 2010, pp. 41-44, Jun-2010.
  69. 84. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs", IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp. 607-611, May-2010.
  70. 83. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Noise-Insensitive Offset Calibration Technique for Time Interleaved SAR ADC", Proc. IEEE International Symposium on Circuits and Systems – LASCAS 2010, , Feb-2010.
  71. 82. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 392-395, Nov-2009.
  72. 81. Cheok-Teng Lei, Seng-Pan U, R. P. Martins, "High-Speed Robust Level Converter for Ultra-Low Power 0.6-V LSIs to 3.3-V I/O", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 396-399, Nov-2009.
  73. 80. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, "On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator", in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC), pp. 49-52, Nov-2009.
  74. 79. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, "Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 333-336, Nov-2009.
  75. 78. Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Modified Charging Algorithm for Comparator-Based Switched-Capacitor Circuits", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 86-89, Aug-2009.
  76. 77. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Comparator-Based Successive Folding ADC", IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 117-120, Jan-2009.
  77. 76. Kim Fai Wong, Ka Ian Lei, Seng-Pan U, R. P. Martins, "1-V 90dB DR Audio Stereo DAC with Embedding Headphone Driver", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp1160-1163, Dec-2008.
  78. 75. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1192-1195, Dec-2008.
  79. 74. Li Ding, Sio Chan, Kim Fai Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Pseudo-Differential Comparator-Based Pipelined ADC with Common Mode Feedforward Technique", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 276-279, Dec-2008.
  80. 73. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1164-1167, Dec-2008.
  81. 72. Ngai Kong, Seng-Pan U, R. P. Martins, "Novel CMOS Switched-Current Mode Sequential Shift Forward Inference Circuit for Fuzzy Logic Controller", in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 396-399, Dec-2008.
  82. 71. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs", in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008, pp. 642-645, Sep-2008.
  83. 70. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier", ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5-8, Aug-2008.
  84. 69. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs", in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008, pp. 922-925, Aug-2008.
  85. 68. He Gong Wei, Chon-Kit Lai, Seng-Pan U, R. P. Martins, "A 100MS/s Recycling 2-Step ADC Embedding Programmable Gain Amplification for DVB Satellite", the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 132-135, Aug-2007.
  86. 67. Ngai Kong, Seng-Pan U, R. P. Martins, "A Novel Reconfigurable Membership Function Circuit for Analog Fuzzy Logic Controller", Proceedings of 20th China Symposium on Circuits and Systems – CSCAS 2007, pp. 163-168, Jun-2007.
  87. 66. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1947-1950, May-2007.
  88. 65. Ka Hou Ao Ieong, Seng-Pan U, R. P. Martins, "A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique", IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 183-186, Dec-2006.
  89. 64. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications", Proceedings of RIUPEEEC (Macao, China), pp. 105-108, Jul-2006.
  90. 63. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "A Novel Architecture of Comparator-Mismatch-Free Multi-bit Pipeline ADC", Proceedings of the Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), Session of Circuit and System, pp. 129-132, Jul-2006.
  91. 62. Chon-In Lao, Seng-Pan U, R. P. Martins, "An Expandable and Extendable High-Order Semi-MASH Sigma Delta Modulator", Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp. 68-73, Jul-2006.
  92. 61. Ka Hou Ao Ieong, Seng-Pan U, R. P. Martins, "Design of a 1-V 10-bit 120MS/s Current-Steering DAC with Transient-Improved Technique", Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp. 137-140, Jul-2006.
  93. 60. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter", Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp. 133-136, Jul-2006.
  94. 59. Pui In Mak, Seng-Pan U, R. P. Martins, "A 1V 14mW-per-Channel Flexible-IF CMOS Analog-Baseband IC for 802.11a/b/g Receivers", in IEEE Symposium on VLSI Circuits (VLSI), Digest of Technical Papers, pp. 288-289, Jun-2006.
  95. 58. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits", in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3794-3797, May-2006.
  96. 57. Kin-Sang Chio, Seng-Pan U, R. P. Martins, "A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Quantization Level", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1892-1895, May-2006.
  97. 56. Chon-In Lao, Seng-Pan U, R. P. Martins, "A Novel Effective Bandpass Semi-MASH Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 581-584, May-2006.
  98. 55. Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4305-4308, May-2006.
  99. 54. Pui In Mak, Seng-Pan U, R. P. Martins, "Design and Test Strategy underlying a Low-Voltage Analog-Baseband IC for 802.11a/b/g WLAN SiP Receivers", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2473-2479, May-2006.
  100. 53. Pui In Mak, Seng-Pan U, R. P. Martins, "A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-/spl mu/m CMOS", in Proc. of IEEE Custom Integrated Circuits Conference (CICC), pp. 649-652, Sep-2005.
  101. 52. Pui In Mak, Seng-Pan U, R. P. Martins, "A 1V IEEE 802.11a/b/g-Compliant Receiver IF-to-Baseband Chip in 0.35µm CMOS for Low-Cost Wireless SiP", 52nd Edition International Solid-State Circuits Conference – ISSCC 2005, San Francisco, USA, February 2005, and 42nd Edition Design Automation Conference – DAC 2005, Anaheim, California, USA, June 2005, Student Design Contest – Second Place, Conceptual Category" – Referred in IEEE Solid-State Circuits Society Newsletter, Vol.10, No.3, pp.7-8, Sep-2005.
  102. 51. Pui In Mak, Seng-Pan U, R. P. Martins, "Multistandard-Compliant Receiver Architecture with low-voltage Implementation", in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 223-226, Jul-2005.
  103. 50. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel low-voltage circuit techniques for fully-differential reset- and switched-opamps", in Proc. of Ph.D. Research In Micro-Electronics & Electronics (PRIME), pp. 398-401, Jul-2005.
  104. 49. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC", in Proc. of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC), pp. 276-280, Jun-2005.
  105. 48. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits", in Proc.of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 1585-1588, May-2005.
  106. 47. Ka Hou Ao Ieong, Chong-Yin Fok, Pui In Mak, Seng-Pan U, R. P. Martins, "A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 392-395, May-2005.
  107. 46. Chon-In Lao, Seng-Pan U, R. P. Martins, "A Novel Semi-MASH Sub-stage for High-order Cascade Sigma-Delta Modulators", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 3095-3098, May-2005.
  108. 45. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 1581-1584, May-2005.
  109. 44. Kin-Sang Chio, Seng-Pan U, R. P. Martins, "A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3099-3102, May-2005.
  110. 43. Kai-Yiu Che, Hon-Weng Chong, Seng-Pan U, R. P. Martins, "A 1-V 5.12-MHz Sampling-Rate 13-bit CMOS Sigma-Delta Modulator Using Reset-Opamp Technique for Portable Aduio Data Acquistion System", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 186-191, Oct-2004.
  111. 42. Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U, R. P. Martins, "A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Weighted-Averaging for Portable Audio Data Acquisition System", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 180-185, Oct-2004.
  112. 41. Pui In Mak, Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, "A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 221-226, Oct-2004.
  113. 40. Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, "A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 215-220, Oct-2004.
  114. 39. Pui In Mak, Seng-Pan U, R. P. Martins, "A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver", ", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 233-238, Oct-2004.
  115. 38. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS), pp. 138-143, Oct-2004.
  116. 37. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems", Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004, pp. 172-175, Oct-2004.
  117. 36. Ngai Kong, Seng-Pan U, R. P. Martins, "A Novel Current-Mode Reconfigurable Membership Function Circuit for Mixed-Signal Fuzzy Hardware", Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006, pp. 101-104, Jul-2004.
  118. 35. Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, "Modeling of Noise Sources in Reference Voltage Generator for Very-High-Speed Pipelined ADC", in Proc. of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1, pp. 5-8, Jul-2004.
  119. 34. Kin-Sang Chio, Seng-Pan U, R. P. Martins, "A Novel Low-Voltage 2nd-Order Sigma-Delta Modulator with Double-Sampling for GSM/DECT/WCDMA", in Proc. of International Conference on Communications, Circuits and Systems (ICCCAS), vol. 2, pp. 1146-1150, Jun-2004.
  120. 33. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems", in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. I-369 – I-372, May-2004.
  121. 32. Pui In Mak, Seng-Pan U, R. P. Martins, "A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications", ", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 417-420, May-2004.
  122. 31. Pui In Mak, Kin-Kwan Ma, Weng Ieng Mok, Chi-Sam Sou, Kit-Man Ho, Cheng-Man Ng, Seng-Pan U, R. P. Martins, "An I/Q-Multiplexed and OTA-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 1068-1071, May-2004.
  123. 30. Pui In Mak, Seng-Pan U, R. P. Martins, "A Front-to-Back-End Modeling of I/Q Mismatch Effects in a Complex-IF Receiver for Image-Rejection Enhancement", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 631-634, Dec-2003.
  124. 29. Pui In Mak, Chi-Sam Sou, Seng-Pan U, R. P. Martins, "Frequency-Downconversion and IF Channel Selection A-DQS Sample-and-Hold Pair for Two-Step-Channel-Select Low-IF Receiver", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 2, pp. 479-482, Dec-2003.
  125. 28. Pui In Mak, Seng-Pan U, R. P. Martins, "A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver", in Proc.of International Conference on ASIC (ASICON), vol. 1, pp. 573-576, Oct-2003.
  126. 27. Chon-In Lao, Seng-Pan U, R. P. Martins, "Bandpass Sigma-Delta Modulator SIMULINK® Non-Idealities Model with Behavior Simulation", Proc. International Conference on ASIC – ASICON 2003, pp. 203-206, Oct-2003.
  127. 26. Pui In Mak, Weng Ieng Mok, Seng-Pan U, R. P. Martins, "I/Q Imbalance Modeling of Quadrature Transceiver Analog Front-Ends in SIMULINK", in Proc. of IEEE International Conference on Vehicular Technology, vol. 4, pp. 2371-2374, Oct-2003.
  128. 25. Chon-In Lao, Ho-Ieng Ieong, Kuai-Fok Au, Kuok Hang Mok, Seng-Pan U, R. P. Martins, "A 10.7-MHz Bandpass Sigma-Delta Modulator using Double-Delay Single-Opamp SC Resonator with Double-Sampling", in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS), vol. 1, pp. 1061-1064,, May-2003.
  129. 24. Seng-Pan U, Sai Weng Sin, R. P. Martins, "Spectra Analysis of Nonuniformly Holding Signals for Time-Interleaved Systems with Timing Mismatches", in Proc. of IEEE Instrumentation and Measurement Technology Conference (IMTC), vol. 2, pp. 1298-1301, May-2003.
  130. 23. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Timing-Mismatch Analysis in High-Speed Analog Front-End with Nonuniformly Holding Output", in Proc. of IEEE International Symposium on Circuits and Systems 2003 (ISCAS), vol. 1, pp. I-129 – I-132, May-2003.
  131. 22. Pui In Mak, Seng-Pan U, R. P. Martins, "A Novel IF Channel Selection Technique by Analog-Double quadrature Sampling for Complex Low-IF Receivers", in Proc. of International Conference on Communication Technology (ICCT), vol. 2, pp. 1238-1241, Apr-2003.
  132. 21. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Quantitative Noise Analysis of Jitter-Induced Non-Uniformly Sampled-And-Held Signals", in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), vol. 6, pp. VI_253-VI_256, Apr-2003.
  133. 20. Fan Lou, Seng-Pan U, R. P. Martins, "N-Path Multirate Sigma-Delta Modulator For High Frequency Application", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 1, pp. 315-318, Sep-2002.
  134. 19. Fan Lou, Seng-Pan U, R. P. Martins, "Mismatch-Insensitive N-Path Multirate Sigma-Delta Modulator for High-Frequency Applications", in Proc. of 45th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1, pp. I-360-I-363, Aug-2002.
  135. 18. Seng-Pan U, R. P. Martins, J.E.Franca, "Design and Analysis of Low Timing-Skew Clock Generation for Time-Interleaved Sampled-Data Systems", of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 441-444, May-2002.
  136. 17. Seng-Pan U, R. P. Martins, J.E.Franca, "A 2.5V 57MHz 15-tap SC bandpass interpolating filter with 320MHz output sampling rate in 0.35/spl mu/m CMOS", IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, vol. 45, no. 1, pp. 380-381(& 475), Feb-2002.
  137. 16. Seng-Pan U, Ho-Ming Cheong, lu Leong Chan, Keng-Meng Chan, U-Chun Chan, Mantou Liu, R. P. Martins, J.E.Franca, "An SC CCIR-601 Video Restitution Filter with 13.5 MSample/s Input and 108 MSample/s Output", in Proc. of IEEE International Conference on ASIC (ASICON), pp. 374-377, Oct-2001.
  138. 15. Seng-Pan U, "A Novel Frequency-Translated Filtering Technique for DDFS Systems and its Integrated Circuit Implementation", in Proc. of The 4th China Association Science and Technology (CAST) Conference of Young Scientists, pp. 46-47, Oct-2001.
  139. 14. Seng-Pan U, R. P. Martins, J.E.Franca, "A High-Speed Frequency Up-Translated SC Bandpass Filter With Auto-Zeroing For DDFS Systems", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 320-323, May-2001.
  140. 13. Seng-Pan U, R. P. Martins, J.E.Franca, "High-Frequency Low-Power Multirate SC Realizations For NTSC/PAL Digital Video Filtering", IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 204-207, May-2001.
  141. 12. Seng-Pan U, R. P. Martins, J.E.Franca, "Experimental Results of SC Fractional Multirate Converters with Intermittent Polyphase Structures", in Proc. of the First Portugal-China Workshop on Solid-State Circuits, pp. 28-29, Oct-2000.
  142. 11. Seng-Pan U, R. P. Martins, J.E.Franca, "A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction", IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 177-180, May-2000.
  143. 10. Seng-Pan U, Neves, R., R. P. Martins, J.E.Franca, "A 120 MHz SC 4th-Order Elliptic Interpolation Filter with Accurate Gain and Offset Compensation for Direct Digital Frequency Synthesizer", The First IEEE Asia-Pacific Conference on ASICs (AP-ASIC’99), pp. 1-4, Aug-1999.
  144. 9. Seng-Pan U, R. P. Martins, J.E.Franca, "High Performance Multirate SC Circuits with Predictive Correlated Double Sampling Technique", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2, pp 77-80, May-1999.
  145. 8. Seng-Pan U, R. P. Martins, J.E.Franca, "Highly Accurate Mismatch-Free SC Delay Circuits with Reduced Finite Gain and Offset Sensitivity", in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 2, pp 57-60, May-1999.
  146. 7. Seng-Pan U, R. P. Martins, J.E.Franca, "A Novel Half-Band SC Architecture for Effective Analog Impulse Sampled Interpolation", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol.1, pp 389-393, Sep-1998.
  147. 6. Seng-Pan U, "A Novel Impulse Sampled Interpolation Technique for Efficient and Accurate Analog Multirate Signal Processing", in Proc. of The 3rd China Association for Science and Technology (CAST) Conference of Young Scientists, , Aug-1998.
  148. 5. Seng-Pan U, R. P. Martins, J.E.Franca, "Impulse sampled intermittent polyphase SC FIR rational decimators with double-sampling", in Proc. of IEEE Midwest Symposium on Circuits and Systems, Vol. 2, pp 977-980, Aug-1997.
  149. 4. Seng-Pan U, R. P. Martins, J.E.Franca, "Intermittent Polyphase SC Structures for FIR Rational Interpolation", in Proc. of IEEE International Symposium on Circuits and Systems 1997 (ISCAS), Vol. 1, pp 121-124, Jun-1997.
  150. 3. Seng-Pan U, R. P. Martins, J.E.Franca, "New Impulse Sampled IIR Switched-Capacitor Interpolators", in Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), Vol. 1, pp 203-206, Oct-1996.
  151. 2. Seng-Pan U, R. P. Martins, J.E.Franca, "Switched-Capacitor Finite Impulse Response Interpolators without the Input Sample-and-Hold Filtering Effect", IEEE Midwest Symposium on Circuits and Systems (MWSCAS), Vol. 1 , pp 145-148, Aug-1996.
  152. 1. R. P. Martins, Pong Chi Wai, Seng-Pan U, "UMCHIP - First Integrated Circuit designed in Macau (Multifunctional & Mixed A/D - 1.2µm CMOS)", Proc. Int. Conf. on Education, Practice & Promotion of Computational Methods in Engineering using Small Computers - EPMESC-V, pp. 1583-1589, Aug-1995.
Books and Book ChaptersTotal: 4
  1. 4. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters", Analog Circuits and Signal Processing, Springer, Oct-2010, 978-90-481-9709-5
  2. 3. Pui In Mak, Seng-Pan U, R. P. Martins, "Analog-Baseband Architectures and Circuits - for Multistandard and Low-Voltage Wireless Transceivers", Analog Circuits and Signal Processing, Springer, Sep-2007, 978-1-4020-6432-6
  3. 2. Seng-Pan U, R. P. Martins, J.E.Franca, "超高頻多速開關電容電路設計", 科學出版社, Jan-2007, 7030182499
  4. 1. Seng-Pan U, R. P. Martins, J.E.Franca, "Design of Very High-Frequency Multirate Switched-Capacitor Circuits - Extending the Boundaries of CMOS Analog Front-End Filtering", The International Series in Engineering and Computer Science - Analog Circuits and Signal Processing, Springer, Sep-2005, 978-0-387-26121-8



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